1. Field of the Invention
The present invention relates to a low-voltage differential signaling (LVDS) receiver circuit, and more particularly to an LVDS receiver circuit which has a simple structure but is still able to obtain a large voltage gain.
2. Description of the Related Art
LVDS technology is commonly used to provide a low-power and low-voltage alternative to other high-speed I/O interfaces, specifically for point-to-point transmissions, such as those used in network devices within data and communication networks. It is common practice that LVDS is implemented in ICs to overcome some deficiencies with previous I/O interface circuitry. As the input differential voltage of the LVDS receiver is very small (about 100 mV to 200 mV), and the switching speed of the input signal is very high (greater than 400 MHz), some of issues need to be considered when an LVDS receiver is being made. First, the circuit needs enough voltage gain. Second, the circuit needs to convert a differential output voltage to a single output voltage. Third, the circuit needs to convert a single output voltage to a normal logic level. Fourth, in order to enhance the switching speed, the amplifier circuit should be simple. Fifth, in order to work with the wide ranges of input voltage and supply voltage, the dynamic range of the amplifier should be kept large. Sixth, in order to implement the circuit with a normal CMOS process, the circuit should be robust enough to withstand the process variation and should not require any special process, such as low VTH transistor or high-resistance polysilicon.
As shown in FIG. 1, U.S. Pat. No. 6,788,142 discloses a wide input range amplifier circuit 10, which includes a pre-amplifier stage 11 and a current mode logic stage 12. VDD1 is a 2.5-volt I/O voltage, VDD2 is a 1.2-volt core voltage used for the digital core, and Vcm is ideally set to VDD1/2. Although the prior art circuit 10 satisfies the first requirement, it does not satisfy the other requirements, especially the second one.
As shown in FIG. 2, U.S. Pat. No. 6,512,400 discloses a comparator 20, which includes a differential amplifier 21 and an output inverter amplifier 22. Although the prior art comparator 20 satisfies the second requirement, it needs an additional bias voltage VBB, which cannot be easily made to work for all the input voltage range and process variations.
U.S. Pat. No. 5,764,086 discloses a circuit having a wide common mode range and a large voltage gain, but that circuit is too complicated to implement. In addition, its speed is too low. Y. Takai, et al., entitled “A 250 Mb/s/pin 1 Gb Double Data Rate SDRAM with a Bi-Directional Delay and an Inter-Bank Shared Redundancy Scheme,” NEC Corp. ISSCC99 WP24.5, pp. 418-419, discloses a circuit having a wide common-mode voltage range, but that gain and its speed is not good enough. U.S. Pat. No. 6,452,429 discloses a circuit having a wide common-mode voltage range and does not require any reference voltage, but that gain and its speed is still not good enough
Though an LVDS receiver can be implemented by combining those two circuits in series, the combined circuit is so complicated that its speed, stability and dynamic range still do not satisfy the above requirements.